Device engineering on advanced Silicon.
I work on the device physics of advanced Silicon CMOS. At Intel that spans front-end-of-line transistor development, middle-of-line, and backside power delivery for advanced CMOS nodes — with earlier work on 18A scribe-line Etest infrastructure and 1T1C embedded DRAM on FinFET. My PhD at Penn State, including a research stint at TSMC, covered 2D and 1D channel materials: the same set of problems from the other direction.
Device representative for the front-end of line on an advanced CMOS node, driving process and integration decisions across the transistor module. Also responsible for the test-structure layouts that feed Silicon decisions.
Device performance lead for backside power delivery on an advanced CMOS node — moving power off the frontside entirely and routing it through the wafer backside instead, which lowers IR drop and frees up frontside tracks for signal-only routing.
Device work on a 1T1C embedded DRAM cell built on FinFET access-transistor technology — a denser, lower-leakage alternative to standalone DRAM for on-die memory at advanced nodes.
Built the Etest data infrastructure and layout automation for target generation across Intel's 18A and 18A-P technologies. Served as the device-side interface to the Product Engineering team — defining what gets measured by the process control monitor (PCM) structures in the scribe line and how that data flows back to Silicon decisions.
Six-month research internship in TSMC's Corporate Research Exploratory Devices and Materials group, advised by Dr. Iuliana Radu and Dr. Matthias Passlack. Worked with random networks of carbon nanotubes, using ultra-low-impedance measurements to extract single-nanotube capacitance and mobility and to drive down interface-trap and defect density — work that fed into IEDM submissions, plus internal tooling: an automated GDS generator and LCR-meter analysis software.
Engineered a selenium interlayer that alloys with palladium during deposition, reducing contact resistance in bilayer WSe₂ FETs and decoupling RC from channel-length scaling. Result was a 3× reduction in contact resistance down to 16 kΩ·µm — foundational outcome of the thesis, published in ACS Nano.
Built an in-memory MoS₂ photodetector that mimics the looming-response neurons in the locust visual system — the device output grows exponentially as a virtual object approaches and spikes at impact. Nature Electronics cover paper, ~300+ citations.
~1,500 total citations across publications in Nature Electronics, Nature Nanotechnology, Nature Communications, ACS Nano, and IEEE IEDM. Coverage in Nature Electronics cover (Vol. 7, Oct 2024), Phys.org, Physicsworld, TechXplore, Daily Mail. Full list on Google Scholar.
Open to conversations on Silicon device physics at the leading edge, advanced memory architectures, and the device-level problems each new node surfaces.